High voltage devices for standard MOS technologies:characterisation and modelling

This work reports on the analysis of high voltage lateral devices. Two different architectures, self-aligned LDMOS and non-self-aligned XDMOS are presented and used in this work. For the separation of the physical effects that take place inside the HV devices the intrinsic drain voltage concept (VK) is proposed. The variation of VK is explained and related to the physical effects inside the device and the charge variation. Through the K point potential, the analysis of the channel and drift resistances is performed function of VG and VD for the whole voltage domain. The several orders of magnitude variation of the resistances is explained by the turning off-on of the intrinsic MOS transistor and also by the depletion of the drift part. The capacitances variation function of the gate voltage, for different drain voltages is discussed in detail taking into account the charge repartition inside the device. It is revealed that the charge transfer between the intrinsic MOSFET and the drift part impacts on the capacitances behaviour resulting in specific peaks on CGS+CGB and CGD characteristics function of VG. The correlation between the capacitances variation and the intrinsic drain voltage VK is demonstrated and it is shown that the formation of the conductive channel in the drift zone is responsible for the decrease of both VK potential and capacitances. A geometrical approximation of the drift zone is presented for the modelling purposes of the HV devices. The electrical approximations that have to be taken into account to build the DC model are also explained. The convergence is granted for the whole voltage domain and no discontinuities were observed for all derivatives. The SMARTSPICE model implementation is compared to the measurements obtained on 100V devices provided by AMI Semiconductor. The accuracy at room temperature shows a RMS error which is less than 6% for the whole voltage domain. The good accuracy of the model is also verified for external temperature variations form room temperature up to 150°C. The scalability of the model for different widths ranging form 10µm up to 250µm is also confirmed. Finally, the impact of self-heating effect on HV devices is clearly studied in these devices. A novel method for the extraction of both RTH and CTH, accounting for the temperature dependence of the thermal resistance, is proposed and validated. The accuracy of the method is verified by calibrated SPICE simulations. The proposed extraction of parasitic thermal network (RTH, CTH) is independent on the device architecture and can be used in any type of HV MOSFETs

APUNTES.LA PINTURA COMO ELEMENTO AUTOBIOGRÁFICO

[EN] This project is a compilation of various works with the objective of showing painting as an autobiographical media. It is, mainly, about painting even though there are other techniques like drawing. The topics vary but, using this memory, we hope to arrange them in conceptual frameworks and by doing so, to create a cohesive and singular vision of this collection.[ES] Realización de un proyecto pictórico constituido por una o varias obras. El proyecto ha de quedar suficientemente definido y objetivado desde el punto de vista técnico y formal, mientras que en el campo de la significación y expresión pictórica ha de atender y reflejar la complejidad de las artes visuales de nuestro tiempo.Anghel, MC. (2020). APUNTES.LA PINTURA COMO ELEMENTO AUTOBIOGRÁFICO. http://hdl.handle.net/10251/144034TFG

Impact of energy performance on transaction prices: Evidence from the apartment market in Bucharest

Purpose – This paper aims to estimate the green premium effect of retrofitted apartments in Bucharest and draw comparisons with international examples. Design/methodology/approach – A geo-referenced transaction database including information on whether the property had been retrofitted is utilised. The paper uses two approaches to test the green premium. One is a hedonic model controlled by areas to estimate the price incentive of a green building. The second is a STAR GLS model evaluating the diffusion effect of house prices spatially by sub-market and assessment upon the pricing effect of green characteristics. Findings – The authors’ findings suggest a green premium in two Bucharest areas of between 2.2 per cent and 6.5 per cent. Spatial diffusion effects are shown to contribute positively to house prices, but the unobserved spatial component reduces this effect. Originality/value – This paper is the first to assess price impacts of green characteristics in Bucharest and one of the first analysing green premium using spatial techniques. The analysis is of significance to policymakers and real estate developers

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence

Tunnel FET Based Ultra-Low-Leakage Compact 2T1C SRAM

International audienceIn this paper, an ultra-low-leakage 2T1C compact SRAM is proposed using Tunnel FETs (TFETs). Proposed design utilizes negative differential resistance property of TFETs and capacitor leakage to implement 1T1C latch. Additional 1T read port is added for reading to avoid data stability issues during read operation. Proposed SRAM design is scalable and easily adaptable for lower technology nodes. Ultra-low leakage below 1fA/bit is achieved in the proposed design. Read and write cycle times of sub-2ns and sub-4ns are designed

Tunnel FET Based Refresh-Free-DRAM

International audienceA refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh. This is achieved using negative differential resistance property of TFETs and storage capacitor leakage. uDRAM allows scaling of storage capacitor by 87% and 80% in comparison to DDR and eDRAMs, respectively. Bitcell area of 0.0275$\mu$m$^2$ is achieved in 28nm FDSOI-CMOS and is scalable further with technology shrink. Estimated throughput gain is 3.8% to 18% in comparison to CMOS DRAMs by refresh removal

3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications

International audienceThis paper presents a TFET/CMOS hybrid SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while CMOS for periphery. The simulation extractions for power and speed are done including wiring and device parasitic capacitance from 4Kb SRAM designed in 28nm FDSOI CMOS process using MOSFETs & Tunnel FETs (TFETs). The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. A 0.35 fA/bit memory array leakage current was achieved showing a 14x to 104x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells. Minimum read and write access pulse is evaluated at 1.27ns at sub-1V supply voltage